Exploiting VISA for Higher Concurrency in Safe Real-Time Systems

Worst-case execution times (WCET) of tasks are essential for safe scheduling in hard real-time systems. However, contemporary processors exceed the capabilities of static worst-case timing analysis tools. The Virtual Simple Architecture (VISA) framework shifts the burden of bounding the WCET of tasks, in part, to hardware. A VISA is the pipeline timing specification of a hypothetical simple processor. WCET is derived for a task assuming the VISA. Nonetheless, at run-time, the task is executed speculatively on an unsafe complex processor, and its progress is continuously gauged. If continued safe progress appears to be in jeopardy, the complex processor is reconfigured to a simple mode of operation that directly implements the VISA, thereby explicitly bounding the task's overall execution time by the WCET. In practice, the complex processor finishes tasks much faster than an explicitly-safe simple processor, creating significant slack in the task schedule. In previous work, this slack was exploited to safely lower frequency/voltage for power savings, in systems with only periodic hard-real-time tasks. In mixed systems with periodic and sporadic hard-real-time tasks, as well as soft-real-time tasks, the slack can be exploited for higher throughput and, hence, increased functionality/quality-of-service. This paper explores the throughput benefits enabled by the VISA framework, using both single-threaded and simultaneous multithreading processors. Using 10 tasksets composed from the C-lab benchmark suite (for periodic and sporadic hard-real-time tasks) and MPEG (for soft-real-time tasks), we show that 2.4-16 times more sporadic tasks are accepted using a VISA-protected complex processor versus an explicitlysafe simple processor. No MPEG frames are dropped by the complex processor whereas 67-93% of frames are dropped by the simple processor. Another contribution is demonstrating the feasibility of the